Isscc 2004 / Session 16 / Td

The key design metric in emerging applications such as wireless sensor networks, is the energy dissipated per function rather than clock speed or silicon area. The author’s previous energyscalable FFT ASIC uses an off-the-shelf standard-cell logic library and memory only scaled down to 1V operation [1]. This paper describes a custom real-valued FFT processor that operates over a variety of operating scenarios (programmable FFT length and bit precision) and employs circuit techniques that allow the supply voltage to be deeply scaled into the subthreshold regime for minimal energy dissipation.